AMD K5 Manuale Utente Scaricare il pdf (Pagina 29)

100

18522F/0—Jan1997 AMD-K5 Processor Data Sheet

PRELIMINARY INFORMATION

FLUSH Cache Flush Input

Asserting FLUSH will flush the internal caches. For accep-

tance, FLUSH must meet the required setup and hold times for

one or more clocks. Instruction and data caches will be invali-

dated. Any modified data in the data cache will be written

back. A flush acknowledge cycle will follow the invalidation to

notify external logic that the internal caches have been

flushed. The FLUSH signal is also sampled at the falling edge

of RESET. If sampled Low, the processor will operate in Tri-

State Test mode.

FRCMC Functional Redundancy Check

Master/Checker Input

FRCMC is used to configure the processor as a Master or

Checker. FRCMC is only sampled at RESET. Sampling FRCMC

High configures the AMD-K5 processor for Master mode opera-

tion, and sampling FRCMC Low configures the processor for

Checker operation. The processor follows standard bus proto-

col in Master mode. It floats all outputs, with the exception of

IERR and TDO, in Checker mode. In Checker mode, all signals

are inputs and their values are compared with predicted

values.

HIT Hit Output

The HIT signal is asserted when an inquire cycle hits a valid

line in the instruction or data cache. This signal can be sam-

pled two clock cycles after EADS has been sampled as

asserted.

HITM Hit to a Modified Line Output

The HITM signal is asserted when an inquire cycle hits a modi-

fied line in the data cache. This signal can be sampled two

clock cycles after EADS has been sampled as asserted. HITM

will remain asserted until the modified line has been written

back.

HLDA Hold Acknowledge Output

The HLDA signal is driven to acknowledge a bus hold request.

The bus is floated when HLDA is asserted. HLDA will be

negated one clock cycle after HOLD is negated. (See HOLD.)

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