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Product Errata 53

Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors

25759 Rev. 3.79 July 2009

92 Deadlock In Multi-Processor Systems May Occur When Earlier

Operations Prevent An Older Store From Writing Data

Description

A system deadlock may occur in multi-processor systems under the following conditions:

1. Interrupts are disabled.

2. A store operation occurs to a cacheable memory type.

3. The store is retired but not yet written the data cache.

4. The store is followed by a persistent (infinite) stream of loads while some of the loads are

misaligned.

5. The misaligned loads are to the same cache index as the store (i.e., bits 11:6 are the same).

6. The misaligned loads are continually picked in the cycle preceding the store.

7. The destination cache line of the store is in a state other than modified (i.e., a probe from another

processor to the same address as the store has previously transitioned this line to a shared state).

Potential Effect on System

In the unlikely event that the above conditions occur, the system hangs.

Suggested Workaround

None. This scenario was contrived in a highly randomized synthetic stress test and is not expected to

occur in real systems.

Fix Planned

Yes

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AMD Athlon 6 Specifiche Pagina 53