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76 Product Errata

25759 Rev. 3.79 July 2009

Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors

116 DDR Chip Selects Tristated One Clock Early in Power Down

Mode

Description

When entering DDR Power Down mode with the Power Down Tristate feature enabled, the chip

selects are tristated coincident with the deassertion of the CKE pins, which is a violation of the DDR

specification.

Potential Effect on System

The DRAM enters an invalid state, resulting in unpredictable system operation. This applies only to

Power Down mode when the PwrDwnTriEn bit is set.

Suggested Workaround

Do not enable the Power Down Tristate feature. BIOS should ensure that Dev:2x90[7] remains at the

default value of 0b.

Fix Planned

Yes

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AMD Athlon 6 Specifiche Pagina 76